R-2R DAC

Introduction

I was watching Dave Jones' video about the gaussian destribution of resistors and wondered how accurate you could make an R-2R Digital-to-Analog converter using ordinary 1% metal film through-hole resistors.

R-2R ladders are constructed with two resistor values, one which is twice the value of the other. One value of resistor can be used with the higher value being constructed of two resistors in series, or the lower value by two resistors in parallel.

The tolerance of the resistors used to construct the ladder must be better than (1/2^n)*100%, where n is the number of bits in the ladder, to ensure that there is no more than 1 quantization level of error when the MSB is turned on/off. Therefore by using 1% tolerance resistors, monotonicity can only be guaranteed up to 7bits.

Assuming that the values of resistors on a reel (or cut-tape) have a Gaussian distribution then by measuring a large amount of resistors, a smaller group of resistors with a significantly lower tolerance can be obtained from the center of the distribution.

I figured a resistor value somewhere between 100K and 1Mohm would be 'about right' as with lower resistances the output impedance of the driver circuitry needs to be very low to maintain the linearity of the DAC, and with higher resistances the output buffer needs to have a very high input impedance. Since the circuit will be physically large it may also become sensitive to RF interference if the impedance of the ladder is high.

I ended up buying four hundred 130Kohm, 1% Metal Film 1/8Watt resistors (Multicomp MF12 Series).

Resistor Measurement Method

The two-wire resistance measurement function of the multimeters I have on hand only have a resolution of 10ohms when measuring a 130K resistor. Even if the meter had absolute accuracy to the least significant digit, the resolution would only allow a 13bit DAC to be produced.

Since we are only interested in the values of the resistors relative to each other and not the absolute values, a Wien Bridge can be used to measure the relative values of the resistors with much greater resolution.

The first resistor (DUT) is connected to the circuit and VR1 is adjusted to zero the voltage measured by the meter. The first resistor effectively becomes the reference resistor which all subsequent resistors are measured against. When a different resistor is placed in circuit, the difference in resistance will unbalance the bridge, producing a voltage which is measured by the meter. The resistance can then be calculated from the voltage using the following formula:

Therefore if our supply voltage is 28.00V and 2.45mV is measured across the bridge, we can consider the resistor under test to have a resistance 0.035% higher than the reference resistor. The absolute value of the supply voltage and reference resistor aren't important - what is important is that they remain stable throughout the measurement process.

Using a multimeter with 0.01mV resolution provides a resistance resolution of 0.00014% or 0.18ohm for a 130Kohm resistor.

The accuracy of the measurement is unfortunately worse than the resolution because there are many sources of measurement error:

• Since the voltage to be measured is small (mV), the measurement will have a significant DC offset produced by the Seebeck effect. This can be eliminated by using an AC powersupply and measuring the AC voltage across the bridge however then the measurement becomes subject to AC noise and my test equipment is less accurate when measuring AC voltage compared to DC. In a DC configuration the offset is effectively nulled by adjusting VR1 but care must be taken to prevent heating or cooling parts of the test setup and introducing a further offset. The effect was minimised by simply avoiding touching any metal parts of the probes or resistors before or during measurements.

• The temperature coefficient of the resistors isn't exceptional (50ppm/*C), which is another reason to prevent heating/cooling the resistors before/during measurement.

• The drift of the powersupply voltage over time will affect the measurement, though I only measured a few mV drift over half an hour at 28V output which contributes a negligible amount to the overall error.

• Self-heating of the bridge resistors. The 47K resistors will dissipate 4.2mW each with a 28V supply resulting in a rise of about 0.5*C. The 130K 1/8W resistor (R3) will rise about 0.2*C

• The input impedance of the multimeter will load the bridge and alter the voltage across it.

• The accuracy/linearity of the multimeter.

• Resistance of the test leads.

Measurement Test Rig

A 'probe' was constructed with serrated pogo pins and 4mm banana jacks soldered to a PCB, much the same as Dave Jones had done. I placed the Wien Bridge on a separate PCB which was connected by test leads to the 'probe' so that the resistors would not drift due to the heat from my hand.

I first measured all the resistors using a Uni-T UT71D multimeter. I used the datalogging function of the multimeter in manual acquisition mode allowing me to place the probe on a resistor, wait a second or so for the reading to settle and then press a button to store the reading before moving on to the next resistor. The range was set to 4.0000V instead of 400.00mV as this has a faster settling time (~1second compared to 4-5seconds) and I only wanted to eliminate the outliers in the first pass.

Every 20 or so resistors i'd mark the number (1-400) of a resistor on the paper tape, so I could reference the recorded values back to the individual resistors and also easily restart if I lost track of where I was up to. This took around 15-20 minutes to measure all 400.

The following is the data from the Uni-T meter, in order of measurement and sorted in ascending voltage:

The first observation is that the data shows a roughly normal distribution. Just like Dave's test there are no obvious trends in the value of the resistors as they roll off the production line.

Looking closer we find an unexpected quirk of the Uni-T meter - there are no negative data points smaller than -0.0004V and a suspicious amount of 0.0000V points. I suspect the Uni-T meter suppresses negative voltages from -0.0003V to 0.0000V. Between 0.0092 and 0.0099 is also not well represented and is perhaps a quirk of the ADC in the Uni-T meter. Some of the outliers are probably due to measurement error - bad probe contact or being impatient and pressing the store button before the measurement settled.

Next, 63 resistors from the centre of the distribution were selected to be re-measured. This time I used a Fluke 87V multimeter which has a HighZ mode in the millivolt range - >1Gohm input impedance versus the fixed 10Mohm of the Uni-T. Care was taken to ensure that the probes were making proper contact and that the measurement was repeatable.

The following is the data from the Fluke meter, sorted in ascending resistance assuming a reference resistor of 129.32Kohm

Again there are a couple of outliers even though this batch of resistors were selected from a supposedly linear section of the previous data but this can be assumed to be due to errors in the Uni-T data.

Designing the ladder

To determine the highest resolution monotonic DAC that can be created from the above 63 resistors, the tolerance of groups of resistors needed to construct 10 to 14 bit ladders were calculated. Each column represents the tolerances (in %) of all consecutive groups of resistors which can be used to create a given bit depth ladder. The group with the lowest tolerance for each bit depth is bolded.

The highest resolution monotonic DAC that can be created (assuming no error in the measurements) by placing the resistors randomly is therefore a 12bit ladder, as a 13bit ladder would require a tolerance of 0.012% and the best grouping of 39 resistors is only 0.014%.

Ladders using unequal rungs

There is a method that allows a higher resolution monotonic DAC to be created if the resistances are known (and measured to adequate accuracy).

The ladder is built up rung-by-rung, where the '2R' value of each rung is matched to the sum of the 'R' resistor plus the Thevenin resistance of all the previous (least significant) rungs.

Although the above ladder uses wildly different resistor values, the same technique can be used to compensate for small variations in a group of resistors with the same nominal value.

The only two resistors required to be equal value are the two '2R' resistors in the least significant rung. These should also be around the mean value of the available resistors

Since the resistor for each 'R' position is free to be any value, choice values can be used to 'steer' the Thevenin resistance towards the mean value of the available resistors therefore allowing them to be used efficiently. Otherwise the Thevenin resistance will drift as you move up the ladder and resistor values outside of what is available will be needed.

Complementary resistors (one with a value higher than the mean, one lower) were placed in series to create the '2R' resistors and free up resistors with close-to-mean values to be used in the 'R' positions.

I decided to construct the DAC as 16-bit since I would be using two 8-bit shift registers anyway. I was able to match each rung to better than 1ohm with the available resistors for all but the last rung where an additional trim resistor was required in the 2R position.

The ladder was built up in LTSpice and simulated as each rung was created. By connecting the newly created MSB to a reference voltage and all LSBs to ground, an output voltage of exactly half the reference voltage would confirm that no error was made in the calculations for that rung.

Driving the ladder resistors

Two 74HC595 8bit shift registers would be used to provide a 16bit parallel output for the ladder. The output impedance of the 74HC595 is undocumented but I measured it to be around 50ohm. This would compromise the linearity of the DAC, so a buffer would be required to provide a output impedance less than 1ohm. The following MOSFET buffer is used for each output:

Shoot-through in the input stage (M1 and M3) is limited by R2. Dead time is created in the output stage (M2 and M4) by limiting gate current during turn on - the gates have to charge through R2 but are discharged through the low impedance of the adjacent MOSFET in the input stage, therefore significantly reducing shoot-through current in the output stage.

Ladder output buffer and other design considerations

A high input impedance opamp output buffer is required as the output impedance of the resistor ladder will be R (130K).

As with any non-oversampling DAC it is desirable to also include a low-pass filter to smooth out the steps that occur transitioning from one sample to the next when outputting an AC signal

The positive voltage rail of the shift registers will determine the output swing of the DAC. It should be regulated and be heavily decoupled close to each buffer. I have used a voltage reference, opamp and pass transister to provide a regulated 5V supply for the buffers with a 22uF tantalum capacitor at each buffer and 270uF aluminium polymer cap at every second buffer.

While it is tempting to use 'zero drift' opamps with extremely low input offset voltage to achieve good absolute DC accuracy, these can inject a small amount of switching noise (usually around 10KHz or so) due to the chopping/zeroing circuitry and also create a significant amount of distortion to AC signals. Often the datasheets do not mention if active input offset compensation circuitry is used but if a PSRR plot is provided there is usually a spike at the chopping frequency.

Characterisation

Unfortunately I don't own any DC-coupled test equipment which has 16bits of accuracy however I do have an E-MU 0204 USB sound interface which is AC-coupled and has between 15 and 16 ENOB (effective number of bits).

To test the DAC I used an ATMega328 microcontroller (Arduino) to provide the serial data for a sine wave into the shift registers, and connected the output of the DAC through a 20dB attenuator into the E-MU 0204

The microcontroller plays back a 39 wavelength, 10000 sample continuous sine wave signal. The signal is non-repetitive enough that the noise floor is close to white noise rather than all the noise/distortion occurring at a handful of frequencies.

Arduino Sketch (.zip 116KB)

At first I used a sampling rate of 40KHz however performance was very poor and the buffers were drawing around 10x the shoot-through current simulated in LTSpice, which was enough to produce more than 1LSB of ripple on the 5V voltage rail. I think the MOSFET Spice models I used to simulate weren't accurate (oops!) and I didn't account for the PCB/layout inductance in simulations either.

By lowering the sampling rate to 2KHz and applying a steep digital lowpass at the Nyquist frequency (the DAC has a fixed 5KHz analog lowpass) the following result was achieved:

MATLAB spectrum analysis script and DAC recording (.zip 5.85MB)

An attempt to characterise the DC performance of the DAC at 12bits was made with the Uni-T UT71D multimeter, however a linear sweep showed significant discontinuities occurring at places that could not have been caused by the DAC - i.e. at the transition of LSBs. Not being able to synchronously step the DAC and trigger the multimeter was also a problem.

Update 28/02/2016: DC Characterisation using LTC2400

I purchased a Linear Technology LTC2400 which is a 24-bit ADC with typical performance exceeding 16 effective bits, and guaranteed performance exceeding 15 effective bits at Vref=5V.

The ADC was added to the existing setup with the microcontroller stepping the DAC code and sampling the output with the ADC. The ADC was powered from a 5.1V supply to ensure Vref which is supplied from the 5V reference inside the DAC box does not exceed VCC. Sampled data (28bits - 4LSB are not accurate without oversampling) was output via serial to MATLAB as the system ran through all 16bit DAC codes, 0 to 65535.

The 28bit data was divided by 4096 to obtain data with 16bit scaling. The data was then fitted to an ideal linear response line through the end points allowing integral non-linearity (INL) and differential non-linearity (DNL) to be calculated.

INL was measured to be 2.568LSB, therefore the DAC exceeds 14bits of linearity. DNL was 1.996LSB, making the DAC monotonic at 15bits (just barely). The gain error is 0.000137, while offset error is somewhat high at 8.35LSB though this is likely due to the type of opamp used to buffer the R-2R ladder output. It is obvious from the INL plot that the non-linearity is dominated by the errors in the ladder resistances of the 3 most significant bits. Knowing this, it would be possible to add trimming resistors to trim the values of the MSBs to improve linearity beyond 15bits.